As a semiconductor device becomes smaller and more highly integrated, the memory capability is increased. However, the high integration of the device increases a chip area but decreases a cell area. The reduction of the cell area decreases an area of a cell capacitor. As a result, the read-out capability of the cell is reduced, the durability is degraded by soft errors of alpha particles, and a sensing margin of a sense amplifier is decreased. Therefore, a method for securing a sufficient capacitance in a limited cell region is required.
The capacitance refers to a capacity of charges stored in a capacitor. As a capacitance becomes larger, more information can be stored. The capacitance is represented by Equation 1.
                    C        =                  ɛ          ⁢                      A            d                                              Equation        ⁢                                  ⁢        1            
∈ is a dielectric constant determined by kinds of dielectric films disposed between two electrodes, d is a distance between the two electrodes, and A is an effective surface of the two electrodes. Referring to Equation 1, as ∈ is larger, d is shorter between the two electrodes and A of the two electrodes is increased, the capacitance of the capacitor can be increased. The electrode structure of the capacitor is changed to have a three-dimensional type such as a concave structure and a cylinder structure, thereby increasing the effective area of the electrodes.
FIGS. 1a to 1e are cross-sectional views illustrating a conventional method of fabricating a semiconductor device. A buffer oxide film 110, an etch stop film 115, an interlayer insulating film 120 and a hard mask layer 130 are sequentially formed over a semiconductor substrate 100 including a storage node contact plug 105. A silicon oxynitride (SiON) film and a photoresist pattern (not shown) defining a storage node region are formed over hard mask layer 130. Buffer oxide film 110 plays a role of compensating non-uniformity of semiconductor substrate 100. Etch stop film 115 includes a nitride film having the etching selectivity over interlayer insulating film 120 to stop an etching process.
Referring to FIGS. 1b to 1d, a silicon oxide nitride film (not shown) and hard mask layer 130 are sequentially etched using photoresist pattern as a mask. The oxynitride film and the photoresist pattern are removed. Interlayer insulating film 120 is etched using hard mask layer 130 as an etching mask to form a storage node region 117 that exposes etch stop film 115. Exposed etch stop film 115 at the bottom of storage node region 117 and underlying buffer oxide film 110 are sequentially etched to expose storage node contact plug 105. A first conductive layer 150 is formed over semiconductor substrate 100 including storage node region 117.
Referring to FIG. 1e, first conductive layer 150 is planarized until interlayer insulating film 120 is exposed. A full dip-out process is performed to remove interlayer insulating film 120, thereby forming a cylinder-type lower storage node 152. In the dip-out process, a space margin is insufficient to cause a leaning phenomenon of lower storage node 152.
However, as a height of a capacitor electrode is increased, a thickness of the interlayer insulating film is increased. As a result, an etch depth is deepened when the interlayer insulating film is etched so that it is difficult to secure a lower line-width of the storage node region. Although the buffer oxide film and the etch stop film prevent a leaning phenomenon of the cylinder-type lower storage node, a sufficient depth is not secured to prevent the leaning of the capacitor.